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L1, L2 and L3 Cache's on CPU's

Discussion in 'A+' started by morph, Aug 21, 2007.

  1. morph

    morph Byte Poster

    Just somthing i've been wondering, ovbiously the early cpu's didnt have L2 or L3 caches, whilst reading up about all this the more modern cpu's have an L3 cache, for example on the Intel Itanium 2 its got an L3 cache of 1.5meg-3meg whereas its L1 cache is 32kb - why isnt the L1 cache the biggest so the cpu goes there first? Or am i missing somthing ovbious (which wouldnt surpise me ) :)
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  2. Fergal1982

    Fergal1982 Petabyte Poster

    So there you have it. Check out the rest of the article for more detailed information on the caches.
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  3. greenbrucelee
    Highly Decorated Member Award

    greenbrucelee Zettabyte Poster

    When the cpu is using lots of bits of data the cpu needs to access the ram, but ram isnt fast enough so the CPU uses cache the Level 1 cache is the first one used then the 2nd then the 3rd.

    The reason why the L1 cache is smaller than the L2 is because a smaller level 1 cache and a bigger level 2 cache make the cpu (pipelining etc) much more efficient
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  4. morph

    morph Byte Poster

    ah ok cool :) ta
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  5. dmarsh

    dmarsh Terabyte Poster

    Firstly thats a very good question ! :biggrin

    The not fast enough bit is to do with latency, however it could be possible to do away with some of the latency but that would up the cost.
    The latency is related to how physically fast the memory and bus systems are, this is also affected by physical distance.
    Faster memory and better bus connections cost more, thats why the caches get bigger and slower, its the best way to get the most bang for buck.
    Much of the design of things in modern computing is to do with issues relating to latency, if the processor, memory and disk subsystems were closer matched then we
    wouldn't bother with extra design features like level 3 caches.

    The presence of the cache is also to do with the architecture, see Von Neumann bottleneck.

    The cache levels also refer to how close they are to the processor. Level 1 cache is 'on-chip' cache, as such it uses up valuable real estate on the silicon. There are only so many transistors that can fit within a set area, transistor count is based on the size of the die and the size of the gates or density. The bigger the die the more waste as impurities will cause more faulty units and a lower yield. More transistors allow for more complex and powerful processors, so making the level 1 cache bigger could be detrimental to the overall design, as it would use transistors that could be used for other logic or lower the yield by increasing the die size.

    Moores law covers alot of this, many people think they understand moores law as they have the media's attention deficit disorder definition, they generally don't.

    Moores Law :-


    Caches in general :-


    Design is the careful balancing of multiple forces or variables.

    So on one level you are right, its just that your processor design would probably cost you £10,000, and it might not scale as well as 10 x £1000 processors ! :biggrin

    Of course you can also pay for the extra complexity, it works fine on a SISD architecture, as soon as you bring in multiprocessor architectures you have cache snooping and cache coherency to deal with.

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