CPU help about stages and pipelines

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Hello!

I have a question regarding the stages in Pipelining inside a cpu, I quote from the Mike Meyers book for the 220-601 exams regarding processors

"After the pentium, pipelines kept getting longer, reaching up to 20 stages in the pentium. Since then, Intel and AMD have kept CPU pipelines to around 12 stages (although this could change again)"

I read through the rest of the pages regarding pipelines and stages etc, I couldn't find the answer to what was nagging away to me in my head, the more stages a pipeline has the more clock cycles it takes data to go through the pipeline? or is the circuitry inside the cpu at such a microscopic level that this isn't the case...? I still take into account the longer pipelines have the advantage of being less likely to stall from complex calculations but I'm not sure in terms or speed. To me it sounds to be true but I don't want to assume these kind of things as I have no previous experience of this kind of work

I'm hoping that my assumption is right on this one , this being my first load of studying makes me think I know less about computers than I originally thought but is making me more eager to read the book thoroughly realising how much I do need to learn

 

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Think about the simple scenario of a 3 stage process load/decode/execute.
Assuming each of these processes takes 1 clock cycle it works like this without pipelining
1. load A
2. decode A
3. execute A
4. load B ......

with 3 stage pipelining it's more like
1. load A
2. load B, decode A
3. load C, decode B, execute A
4. load D, decode C, execute B

If you extrapolate those you'll see it's 3 times as fast.
In real life not all instructions are 1 clock cycle long otherwise it would make sense to have as many stages as possible. If you have too few stages there's going to be a lot of stalls, if you have too many stages it'll take longer (relatively speaking) to recover from each stall.

 

thank you for that reply thats answered my question nicely, ta