CLK Cycle

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I used the RISC example to simplify the point that I was trying to get across. Yes, what you say is true and there are ongoing developments to make instruction sets more efficient. At a point in time, though, RISC machines where developed to break down more complex instructions into their component parts for much faster execution.

 

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Hopefully this might shed some light on the matter :-

http://arstechnica.com/articles/paedia/cpu/pentium-1.ars

As you will see in a modern processor while it may be possible to determine the number of cycles an instruction may take, this bears very little resemblance to anything because of the various agressvie optimisations that may or may not happen.

 

Left book at home today will post quote tonight, I think you are thinking to deep its meant to be basic pipe lines are further on in the chapter. Just wanted to know if i was thinking along the right lines.

 

How does this disregard anything I've said?

 

Hi Mathmatix
i wasn't disregarding what you said, i was wondering why there is a min of 2 cycles in very early cpu's
and was it simply counting taking from the external date bus and putting back was this the min, because it dosnt seem to take into account for the regesters or im i just being stupid

 

There *are* CPUs about with just one clock cycle for an instruction.
I mentioned the 6502 earlier, but my memory seems to be at fault - when I checked the quickest instruction is 2 cycles.

Do a search on "sungle cycle instructions".

Harry.

 

Not dissing anythin you said !

The article I posted is a good overview of the pentium architecture since its incepetion, and along with some of the other information people have posted probably is more useful to understand than arbitary instruction timings.

The following point I was making was that assembler programmers used to use instruction cycle counts to tune their algorithms and work out what would be a more efficient implementation, while this is still possible to some extent the processor optimisations make it a much less straight forward proposition. Therefore knowing these counts is less useful than it used to be. You would probably need to profile important algorithms just to be sure about their relative performance on any given architecture.

The drive for RISC was largely to create processors with ALL single cycle instructions as the articles I posted point out. Harry is correct in stating that single cycle instructions exist/ed both pre, during and post RISC.

http://www.heyrick.co.uk/assembler/riscvcisc.html

In fact post RISC designs with heavy optimisation mean modern hybrid processors can effectively execute some instructions in ZERO cycles, all the optimisations mean that looking at individual instructions in most cases is no longer meaningful.

 

Thank you Dmarsh26
this is the quote from the Myers book

well i meant the quote you gave