1. This site uses cookies. By continuing to use this site, you are agreeing to our use of cookies. Learn More.

Cpu to Address Bus.

Discussion in 'A+' started by st giles, Sep 6, 2005.

  1. st giles

    st giles Nibble Poster

    54
    0
    23
    Hi there.
    Am currently wading through the chapter on cpu's and am a bit miffed :unsure . Regarding the man in the box ( mike meyers book this is ) he's working away and the clock cycle alerts him to more info coming in to be processed. He's just finished doing his previous calculation. How does he know what data he wants from the ram next as he has to put it onto the address bus in order to tell the northbridge what to retreive.
    What im really trying to say is how does he know what he wants until he gets it????. Or is it me being silly :oops:
     
    Certifications: none
    WIP: a+
  2. st giles

    st giles Nibble Poster

    54
    0
    23
    Me thinks i must be asking a silly question then :hhhmmm
     
    Certifications: none
    WIP: a+
  3. simongrahamuk
    Honorary Member

    simongrahamuk Hmmmmmmm?

    6,199
    125
    199
    I dont think it is a silly question, I just haven't figured out an answer to it yet!

    My initial thoughts were bi-directional communication, i.e the processor asks for what it wants next, but then I though that I wasn't sure if it was possible, so I give up thinking about it.

    I'll think more on it when I have time.

    :hhhmmm
     
  4. tripwire45
    Honorary Member

    tripwire45 Zettabyte Poster

    13,493
    179
    287
    Meyers is wording things in a way to make them more user friendly but those of us who haven't read Meyers in awhile have a hard time recalling what he was trying to say. :oops:
     
    Certifications: A+ and Network+
  5. st giles

    st giles Nibble Poster

    54
    0
    23
    Umm. Thanks guys.
    I'm sure it will all become more clearer as i progress :blink .
    I just could'nt work that bit out as it does'nt seem to cover where the whereabouts of that required data comes from that is put on the address bus. I thought that maybe it comes in with the data from the external data bus on the previous fetch. I don't know. I'm probably waffling now. Watch this space guys and gals. More questions to come me thinks. Anyway time for a touch of pure genius :morebeer
     
    Certifications: none
    WIP: a+
  6. hbroomhall

    hbroomhall Petabyte Poster Gold Member

    6,623
    115
    224
    Not really silly. The problem is that the author is simplifying so much that lots have been left out. I'm on this chapter at the moment and I can see why you are confused!

    First - he has missed out mentioning a really important register, which is in addition to the 4 he does mention, and this is the Instruction Pointer (IP) register. This tells the CPU where to fetch the next instruction from, and is incremented automaticaly.

    The value in the IP is put onto the address bus so the next instruction can be fetched, and at the same time the IP is incremented ready for the next instruction, or part of instruction.

    Does this help at all? (FWIW I used to do machine level programming, which is why I'm familiar with this area.)
     
    Certifications: ECDL A+ Network+ i-Net+
    WIP: Server+
  7. glytch

    glytch Nibble Poster

    50
    0
    23
    Hi St. Giles!
    I have just finished the chapter on cpu's and I agree with tripwire, Mike has simplified things a lot just to get the concept of how the cpu gets it's data. It's not needed for him to simplify every function, only those that you need to know to have a general idea of how it works (what the address bus and registers are used for).

    When you get to the chapter on RAM, it will become clearer when you learn about bytewide, parity bits etc. (I just finished the chapter myself).

    hope this helps a little

    Andy
     
    Certifications: none yet
    WIP: CompTIA A+
  8. st giles

    st giles Nibble Poster

    54
    0
    23
    Thanks guys,
    That is much more crystal now. :)
     
    Certifications: none
    WIP: a+

Share This Page

Loading...